1. Field of the Invention
The present invention relates to a data recovery method and a data recovery circuit for restoring serially transferred data, a data transmitting/receiving apparatus and an information processing apparatus.
2. Description of the Related Art
Recently, along with an increasing demand for a large-size, high-speed data transmission between devices, boards or chips, various high-speed interface such as USB ((Universal Serial Bus), Serial ATA, IEEE1394, 1G/10G Ethernet (registered trademark), InfiniBand, RapidIO, Fibre Channel and PCI Express, have been proposed, put in practical use, and thus, a tendency for a higher transmission speed and a larger transmission data size may increase also in future.
Many of these high-speed interfaces apply a serial transfer way, in which data is transmitted in synchronization with a predetermined frequency clock signal. The clock signal of the frequency is embedded in data to transfer (embedded clock signal), and, on a reception side, the clock signal is extracted from the reception data, and the reception data is restored with the use of the extracted clock signal (for example, see Japanese Laid-open Patent Application No. 2004-128980). A circuit carrying out such operation is called a clock data recovery circuit (simply referred to as CDR: Clock Data Recovery, hereinafter).
In CDR in the related art, PLL (Phase Locked Loop) circuit is commonly used. VCO (Voltage Controlled Oscillator) included in PLL is controlled in such a manner as to be in synchronization with a phase of the reception data, and a reproduction clock signal is extracted. Then, the reproduction clock signal is used as a reference clock signal, the reception data is latched, and thus, the reception data is accurately restored.
However, as a data transfer rate improves for the purpose of achieving recent high speed data transfer (for example, as the data transfer rate exceeding Gbps order), the oscillation frequency of VOC exceeds Gbps order, and, achieving the CDR circuit having a function of restoring such high-speed data may be difficult. Further, negative factors such as increase in the chip size, increase in the power consumption, increase in the costs, and so forth, may occur at the same time.
Further, when the data transfer rate increases, wiring delay may become unignorable. Accordingly, device layout, wiring layout and so forth should be considered more carefully. Thus circuit design may become difficult. Further, since characteristics of devices to actually apply may influence this matter much, re-design of layout may be required for each process (and, also, re-design of the circuit itself may be required). Thus, circuit reusability may degrade, and required development time may increase accordingly.
In order to solve the problem, an over sampling type clock data recovery circuit has been proposed (for example, see B. Kim et al., “A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-um CMOS”, IEEE JSSC, December 1990, pp 1385-1394). FIG. 1 shows a circuit configuration of the over sampling type clock data recovery circuit in the related art. A multiphase clock generating part 200 includes PLL, DLL (Delay Locked Loop) or such, and generates mutually equal interval multiphase clock signals from a reference clock signal RefCLK. Flip-flop devices (which may be simply referred to as FFs or F/Fs, hereinafter) 201 input data to their data terminals, input respective clock signals of the multiphase clock signals from the multiphase clock generating part 200 to their clock terminals, and take the input data upon rising up (or decaying down) of the respective clock signals.
That is, data output from FFs 201 is one obtained from sampling of the input data with the clock signals having phases slightly different from each other. A digital PLL 202 detects change timing of the data provided by FFs 201, selects the multiphase clock signal which is in synchronization with the thus-detected change timing, and restores it as a reproduction clock signal RecCLK. Further, the DPLL 202 selects data with the reproduction clock signal RecCLK and a clock signal having a predetermined phase difference therefrom (for example, an opposite phase), and outputs the same. Upon selecting the reproduction clock signal, a filter is applied to smooth the data change timing. A signal processing part (not shown) operates with the use of the reproduction clock signal RecCLK as a reference clock signal. Such a configuration of the CDR circuit may be made of a digital circuit except the multiphase clock generating part, and thus, such a circuit may be relatively easily achieved.
The multiphase clock signals may previously have equal phase intervals therebetween. FIG. 2 shows one example illustrating a problem occurring when the multiphase clock signals do not have equal phase intervals. Here, description is made assuming 4 phases, as one example. In FIG. 2, it is assumed that a phase of a reproduction clock signal CLK2 thus selected delays by Δ from an ideal state. Respective data in the signal processing part operates in synchronization with the reproduction clock signal CLK2.
When the reproduction clock signal is switched to a phase of CLK1 at a timing Tsw, a period of the reproduction clock signal is reduced further by Δ in addition to the original phase difference locally, a set up time Tsu′ in FF cannot be sufficiently ensured, and, at the worst, malfunction may occur. This is because, even though design is made such that equal phase intervals should be provided from the multiphase clock generating part 100, skew (for example, wiring delay, load or such, may influence this matter) in each clock signal, up to the output end of the reproduction clock signal RecCLK, may cause the problem. Such phenomena may become more remarkable when the data transfer speed increases. In order to avoid the problem, possible delay amounts in the respective multiphase clock signals should be adjusted at respective parts, which may be difficult to actually achieve, and thus, the above-mentioned problem may not be completely solved.
Further, a method of applying a phase interpolator in the multiphase clock generating part to adjust the phase has been proposed (for example, see Japanese Laid-open Patent Application No. 2002-190724). By providing the phase interpolator or such, the phases of the multiphase clock signals can be made to have equal intervals.